1. Field of the Invention
The present invention relates to a method for fabricating a dual damascene structure, and more particularly, to a method for fabricating a dual damascene structure by using carbon monoxide (CO) and deionized (DI) water for efficiently cleaning residues in a via hole after an etching process.
2. Description of the Prior Art
A dual damascene process provides a method of forming a metal wire coupled with a via plug as a stack structure. The dual damascene structure is used to connect devices and wires in different layers of a semiconductor wafer and is insulated from other devices by the inter-layer dielectrics (ILD) around it. The copper damascene processes, which incorporate copper as the conductive material of dual damascene structures, are common in the art. The copper damascene processes provide a solution to form a metal wire of semiconductor processes under 0.18 or deep sub-micro micron generations in high integration and high processing speed logic integrated circuit (IC) chip fabrication method. Since copper has low resistance (30% lower than aluminum), better electromigration resistance and low-k materials, it is capable of reducing RC delays between metal wires. Accordingly, copper damascene processes become more and more important in IC processes. Typically, the dual damascene process encompasses trench-first, via-first, partial-via, and self-aligned processes, in which the via-first dual damascene process comprises first defining a via opening in dielectric layers and then defining a trench above the via opening by using several lithographic and etching steps.
Please refer to FIGS. 1-4, which are schematic diagrams of via-first dual damascene process according to the prior art. As shown in FIG. 1, a semiconductor device 10 comprises a substrate 12 having a conductive layer 14, a dielectric layer 18, and a photoresist layer 20 disposed on the substrate 12 form bottom to top. An etching stop layer 16 may also be formed on the surface of the conductive layer 14. A photolithography process is performed to pattern the photoresist layer 20 so as to form a via pattern 22 on the photoresist layer 20.
As shown in FIG. 2, an etching process is performed to remove a portion of the dielectric layer 18 through the via pattern 22, until the surface of the etching stop layer 16, for forming a via hole 24. However, residues 26 are formed on the sidewall or bottom corner of the via hole 24 together with the etching process, wherein the residues 26 usually comprises high-molecule polymers with carbon, silicon, nitrogen, fluorine, titanium, or other impurities. The residues 26 covering the surface of the via hole 24 influence the critical dimension (CD) of following processes and performance of the semiconductor device 10, such as the quality of contact plug in the via hole 24, resulted in reaction chamber memory effect.
With reference to FIG. 3, an ash process is carried out to remove the photoresist layer 20. In the prior art, oxygen (O2) is usually used to remove the photoresist layer 20. In addition, the ash process may be carried out by combining oxygen with nitrogen (N2) or a little amount of tetrafluoromethane (CF4). Although the ash process causes an efficient removal of the photoresist layer 20 and a breakdown of polymer bonds of the residues 26 present in the sidewall at the bottom of the via hole 24, photoresist residues 30 may be newly formed on the dielectric layer 18. However, the ash process is not able to effectively remove the fluorine-containing residues 26. On the other hand, although the process by combining oxygen with 4-5% of CF4 helps to remove the polymer residues 26, the method of removing the photoresist layer 20 that utilizes fluorine-containing gas easily remains fluorine-containing residues 28, 32 on the sidewall or bottom corner of the via hole 24 and the surface of the dielectric layer 18, these residues 28, 30, 32 also affect the performance of following processes and electric quality of contact plug that will be formed later. As a result, liquid solvent having high cost has to be used to clean the semiconductor device 10 in conventional method. After the residues 28, 30, 32 are removed by the high-cost liquid solvent, a trench structure can be formed.
Referring to FIG. 4, a patterned photoresist layer (not shown) is formed on the dielectric layer 18, wherein the patterned photoresist layer has a trench pattern. Thereafter, the dielectric layer 18 is etched through the trench pattern so as to form a trench structure 34 on the upper portion of the dielectric layer 18. Finally, the patterned photoresist layer and a portion of the etching stop layer 16 are removed to expose the conductive layer 14 in the via hole 24, and the fabrication of the dual damascene opening is formed.
As mentioned above, it is easily to remain residues on the surface of the via hole during forming the via hole. In addition, the process of removing the photoresist layer by fluorine-containing gas, such as CF4, also forms residues on the via hole or the dielectric layer. The above-mentioned residues have to be cleaned through using high-cost solvent. Since the costs of solvent or chemical materials are generally one of the keys of semiconductor process cost, how to improve the dual damascene fabrication method to reduce process cost is still an important issue for the manufacturers.